Visual display system

ABSTRACT

An enhanced alphanumeric character display system in which a raster scan dot matrix is generated at a plurality of display locations with local computer control over local groups of displays is disclosed. Data from the generation of an individual dot matrix characters is locally stored in a recirculating register independently from a random access refresh memory thereby removing the recirculation function from the refresh memory. A technique for shifting selected dots in the character matrix to obtain improved characters is also disclosed.

United States Patent Chambers Nov. 20, 1973 [54] VISUAL DISPLAY SYSTEM3,400,377 9/1968 Lee 340 1725 3,597,757 8/1971 Vincent-Carrefour....340/172.5 [75] Invent Derek Chambers Frammgham- 3,528,068 9/1970 Johnson340 324 A Mass 3,609,743 9/1971 340/324 A [73] Assignee: RaytheonCompany, Lexington, 3,653,001 3/1972 Nmke 340/ 172.5

Mass. Primary Examiner-Harvey E. Springborn [22] F'led: May 1971AttrneyMilton D. Bartlett, Joseph D. Pannone, 21 L 143,343 Herbert W.Arnold and David M. Warren 52 us. c1. 340/172.5, 340/324 AD ABSTRACTInt. Cl. An enhanced alphanumeric character system 0' Search A, in araster scan dot matrix is generated at a plu- 340/324 AD rality ofdisplay locations with local computer control over local groups ofdisplays is disclosed. Data from 1 1 Refemnces cited the generation ofan individual dot matrix characters UNITED STATES PATENTS is locallystored in a recirculating register indepen- 3,41s,51s 12/1968 Reese, n340 324 AD demly from a random access refresh memory thereby 5 29 6/1969s 340 removing the recirculation function from the refresh 3,685,0398/1972 Flanagan 240/1725 X memory. A technique for shifting selecteddots in the 3,696,392 10/1972 Fossum 1 2 X character matrix to obtainimproved characters is also 3,701,988 10 1972 Allaart 340 1725 xdisciose 3,505,650 4/1970 Brown, Jr. 340/1725 3,388,391 6/1968 Clark340/1725 ll Claims, 12 Drawing Figures CEN TRAL l2 PROC E SSOR I4 4 "i:1: i

ODEM MODEM ODEM l8 /8 MODEM LOCAL L O C A L co MP 20 HE COM P UTERDISPLAY 24 D IS PLAY 0 24 ONTROLLER CONTROLLER PAIENTEU NOV 20 I975SHEET 18? 4 CENTRAL PROCESSOR R R E YE M M LTI AL E E AU LL W" D n D C UP O O 0 6R M M LW m c w 4 J 6 M M 4 u 2 2 M) 4 u. m w 2 H L m w M i DnnD cwfl m O O O M M L DN w 0 C PATENIEUuuvzo ms 3. 774, l 61 SFEEU 2 CF 4MATRIX I 7x9 E E MATRIX 7x7 MATRIX u ENHANCED I 7 x 7 MATRIX D Q Q Q Q QQ Q 7 NORMAL POSITIONS Q Q Q Q Q Q 6 SHIFTED RosmoNs Q Q DOT SHlFTENHANCED CHARACTER 0 0+ Q Q Q Q Q Q Q Q Q Q QQ o 0 0+ g FIG. 8

VISUAL DISPLAY SYSTEM BACKGROUND OF THE INVENTION This invention relatesto a dot matrix type visual display system in which alphanumericcharacters are developed by a raster type scan on a viewing screen suchas a cathode ray tube.

In many data display and communication systems, such as those used withdigital computers, it has been found useful to display the processedinformation as alphanumeric characters on a cathode ray tube or otherdisplay means. The cost of such a display device is significantlyreduced by the use of a conventional raster scan monitor with a cathoderay tube, which monitor could be a television set without the radiofrequency and intermediate frequency sections. Typically, charactershave been formed in the prior art form a dot matrix in which a clusterof dots form characters on the screen by unblanking the raster sweep ofthe electron beam at selected intervals which correspond to points onthe matrix. Such systems do not produce characters with the resolutionof stroke generators or monoscope systems, as the characters are notcontinuous lines, but rather a plurality of dots. Additionally, becauseof the matrix geometry, true letter shapes are not obtainable from aconventional dot matrix for many characters unless the matrix isexpanded to include more closely spaced dots, with an accompanyingincrease in cost, circuit complexity and bandwidth requirements.

An additional problem in dot matrix visual display systems of the priorart, and of other cursive displays, including those of the targetmonoscope type, is the requirement that a portion of the local computermemory be dedicated to refreshing the display. Thus, interfacecircuitry, such as character entry and readout registers, delay linesand gating circuitry are required to couple data to the display fromthat portion of the local computer memory which forms a portion of therefresh memory.

SUMMARY OF THE INVENTION The above problems and other problems of theprior art are overcome by the present invention, in which an enhanceddot matrix display is developed by a raster scan. In accordance with thepresent invention, the characters to be generated are stored in a readonly memory which is accessed by character address codes that arerecirculated in a recirculating shift register. This shift registercontains sufficient data to generate one line of characters, andrecriculation therein is independent from the local memory, which in theinstant invention is a random access memory. thus, the processor is freeto perform functions other than refreshing the display with a consequentimprovement in system efficiency, cost and circuit complexity.

In the present display, each character, for example, may comprise sevenparallel lines containing seven dots per line for a seven by seven dotmatrix. The top line of dots for all of the characters in the row isgenerated first, then the second, and so forth until the seventh line isgenerated, whereupon several lines are skipped, for example six, and thenew row of characters is generated until a complete frame of lines isdisplayed. Selected dots in the character matrix are laterally displacedfrom their normal position in the matrix by delaying the dot generationsignals by one-half of the interdot space in order that enhancedcharacters are produced. The effeet is the same as if the number of dotsin the matrix were increased, but without the additional circuitcomplexity and bandwidth requisite by such an approach.

BRIEF DESCRIPTION OF THE DRAWINGS Further advantages of the inventionwill become apparent from the following specification taken inconnection with the accompanying drawings wherein like referencecharacters identify parts of like function throughout the differentviews thereof and wherein several of the views double lines indicatedata flow.

FIG. 1 is an overall system block diagram of a visual display systemembodying the present invention;

FIG. 2 is a block diagram of an individual display embodying the presentinvention;

FIGS. 3 through 5 are characters formed by dot mat rices of the priorart;

FIG. 6 is an enhanced dot matrix formed in accordance with the teachingof the present invention;

FIG. 7 illustrates the dot shift in accordance with the presentinvention;

FIGS. 8 and 9 illustrate the formation of a single enhanced character inaccordance with the teachings of the present invention;

FIG. 10 is a detailed block diagram of a dot matrix visual displaysystem in accordance with the present invention;

FIG. 11 is a series of waveforms of various signal generated throughoutthe block diagram illustrated by FIG. 10; and

FIG. 12 is a block diagram of the read only memory employed by the blockdiagram of FIG. 10.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to FIG. I, a datacommunications system embodying the present invention is shown generallyat I0. Digital information in binary form is stored at a centralprocessing unit 'CPU) 12, which may be an IBM type 360 computer, whichis coupled to the individual programmable displays via data lines 14,which may be telephone lines. Input and output modems l6 and 18, whichmay be a Western Electric type 201, respectively transmit and receivedata such as character codes between the central processor 12 and asmall programmable local computer unit 20 which includes a computer,such as a Raytheon type 704 computer.

Each local unit 20 controls a cluster of displays 22 by coupling digitalinformation to a display controller 24. In the present embodiment, eachcontroller 24 controls eight displays; however, the system may beexpanded to accommodate any number of displays 22. Additionally, othermodems, not shown, couple data from the CPU to other locallyprogrammable units similar to unit 20, such that the system isexpandable to many clusters of displays at a plurality of spacedlocations.

While various display configurations are possible, such as a singleoutput channel with one refresh memory, one character generator and aroster-scan monitor interface that is capable of driving two1,000-character monitors or four SOD-character monitors; the preferredembodiment is a fully expandable system with up to eight channels, eachchannel being capable of driving either one 2,000-character display, twoIOOO-character displays, or four 500-character displays.

When more than one television monitor display 22 is connected to anoutput channel, of each local computer unit 20 through a displaycontroller 24, conventional local monitor interface circuitry providesthe keyboard multiplexing, split timing and blanking signals required totime-share the memory and character generator between the displays 22.

Referring now to FIG. 2, a block diagram ofa display controller 24 and adisplay 22 with a keyboard 57 is illustrated generally at 50. A randomaccess display memory 52 at any desired location such as a localcomputer 20 or as shown in display controller 24 stores characteraddress codes sufficient to produce a frame of data on a raster screen.The capacity of random access memory 52 is such that it contains dataframes for a plurality ofdisplays and only a portion ofthe memory isactually used for any one display. In accordance with the presentinvention, the frame storage portion of the random access memoryallocated to each display does not perform any of the refresh function,i.e., character address recirculation, as this is accomplished on a lineby line basis in a recirculating shift register or registers therebyfreeing the random access memory 52 for other processing tasks.

Data changes made by keyboard entries are coupled through the localcomputer interface 54 to the random access memory 52 for characterchanges. Data is coupled a row of character address codes at a time fromrandom access memory 52 to a line store 55 in which data sufficient togenerate one row of the raster display is recirculated andnondestructively coupled to the address inputs of a read only memory 56.The data is recirculated once for each of the scan lines in a row ofcharacters. It is thus apparent that any portion of memory 52 isunnecessary for data recirculation. Hence, more flexibility is effectedin both memory storage space and system operation as independent rowstorage is achieved without reliance on the recirculating randon accessmemory 52 or on any external delay line, although, of course, such aline may be used if desired. Data in dot bit form is generated by theread only memory, with seven of the eight generated dot bitscorresponding to one character slice. The number of character slicesrequired for the generation of particular characters as will bedescribed in more detail with reference to FIG. 10 is coupled to dotshift circuit 58 where selected dots in selected character slices areshifted by one-half space or any desired amount in order to formenhanced characters as described with respect to FIG. I and otherunshifted data along with the shifted data is applied in pulse form tovideo amplifier 60 at the raster display which pulses are used tounblank the raster scan to generate the required dot pattern.Conventional system timing 62 synchronizes the random access displaymemory with read only memory and develops both horizontal and verticalsynchronization for application to the raster display 64.

Referring now to FIGS. 3 through 9, various dot matrices are illustratedand compared with the enhanced dot matrix achieved by the presentinvention. FIGS. 3 through 5 illustrate the best that can be done fordot positioning on the given matrix sizes without using the dot shifttechnique of the present invention. FIG. 6 illustrates the improvementsthat are possible with the 7 by 7 matrix when dot shift technique isused. The minimum dot matrix size for recognizable upper casealphanumeric characters illustrated by FIG. 3 is generally considered tobe one comprising 5 by 7 dots arranged in a matrix of parallel,horizontal and vertical columns of dots. While increasing the number ofdots in the matrix improves resolution. additional storage and videobandwidth are required with the consequent decrease in number ofdisplayed character rows. For monitor type raster displays, a matrixallowing good character quality and the possibility of adding lower casecharacters is desirable. These requirements can be satisfied in a 7 by 9dot matrix such as that illustrated by FIG. 4 in which the upper casecharacters A, O, U, V, W, X and Y are illustrated. When the matrix ofFIG. 4 is used in a conventional unshifted type dot matrix of the priorart to present both upper and lower case characters the upper casecharacters, assuming that they are confined to the upper 7 by 7 dotportion of the matrix leave the lower two rows of dot for the tails ofthe lower case character. The effect on character shape and definitionof such a system is illustrated by FIG. 5 in which the distortion andthe letter shape is clearly apparent.

Referring now to FIG. 6, the characters genrated in accordance with thepresent invention are illustrated. By way of example the letter "A isclearly enhanced by the shifting of several selected dots in the matrixresulting in more legible character shapes which may be produced withoutincreasing video bandwidth or de creasing the number of displayedcharacter lines. Only the addition of one column of bits per characteris required to be stored in the character generator read only memoryalong with the 7 by 7 stored dot matrix to achieve the enhancement shownin FIG. 6. Each of the extra bits located in the far left column of dotsin FIG. 8, is used to control the shifting of all dots in a horizontalline with it for the particular character with which the bit is stored.This enables either the original 7 normal dot positions shown in FIG. 7to be available, or the 6 positions spaced equally between them asillustrated. The letter A shown in FIGS. 8 and 9 is illustrative of theimprovement resulting when character dots are shifted one-half space inaccordance with a delay coding which for a shift could be a logical oneand for no shift a logical zero.

As described with reference to FIG. 10, the shift may be generated upondetection of logical one in the control bit position, for example, acomplementary clock phase may be used to gate the video or a delay ofonehalf bit time introduced through a video delay line as illustrated.Thus, it is to be understood that while the video delay line techniqueis described either a complementary clock or other means for delayingselected dots in particular character portions or slices may be used inaccordance with the present invention.

Referring now to FIG. 10, a block diagram of a dot matrix charactergeneration system in accordance with the present invention is showngenerally at 100. A keyboard 102 containing the usual complement ofcharacter and function keys is present at each display 22 to enable anoperator to have access to the local com puter for changing theinformation displayed on the display screen by the activation ofselected keys. When a key on the keyboard 102 is depressed an interruptsignal is coupled to the local computer via line 104 to enable thecomputer to receive data or instruction depending on whether a characterkey or a function key has been depressed.

The keyboard interface gating 103 is of well known design, withcharacter data from a standard keyboard matrix being coupled in an eightbit code to keyboard gating 105 along with a strobe pulse on line 107 togate keyboard data from gating 105 to the local computer via lines 109and into memory 106. Additional keyboard interface gates 111, 113, 115and 121 allow internal timing pulses to clock the keyboard status toenable the transfer of data out of gating 105 in accordance with thestrobe timing. The actual data clocking is provided by timing 127 whichtimes a flip-flop 119 to gate the generated interrupt signal to thelocal computer to allow data to be strobed in.

Keyboard data is stored in a refresh memory such as random accessdisplay memory 106, which memory is capalbe of storing keyboard datafrom a plurality of displays, thus for eight displays storing 2,000characters each, 8K 16 bits of memory is required. In the illustratedembodiment, memory 106 is shown as storing data for one display,however, it may be easily expanded to accommodate any number ofdisplays. Typically six or seven bits of data per character are requiredwith an eighth bit for a movable cursor, with 7 bits resulting in up to128 different character codes. In the illustrated embodiment, a 7 bitcharacter code is employed with the eighth bit reserved for a cursor. Acomplete frame of data of, for example 24 rows of 80 characters per rowwith 16 character spaces for horizontal retrace being 64 characters perrow may be stored and recirculated through memory 106 which, in theillustrated embodiment, is capable of storing 1,024 16-bit words withtwo 8-bit characters comprising each 16-bit word.

In order to access the memory 106 from the local computer, address linesillustratively shown at 108 from the local computer are coupled viaswitch 110 through a gate 112 into the address lines 114 of the randomaccess memory 106 which comprise 10 lines capable of addressing [,024word locations in the memory. Alternatively, the memory 106 may beaddressed from an address counter 116 to be described via gate 112.Memory select logic 118 is activated by a decode signal on line 129 fromthe local computer when data is required to be written or read from thedisplay memory and activation of memory select 118 serves to inhibitdata from address counter 116 and switches gate 112 to allow addressdata from the local computer via switch 110 to be coupled to the memory106. When data is present on the display screen, address counter 116sequentially addresses each word location in the memory as controlled bythe RAM timing 117 to be described and the display timing which RAMtiming is typically approximately 1 microsecond per charcter.

A recirculating memory, row store 120 is loaded a row at a time which inthe present embodiment comprises 64 characters and 16 retrace intervalsfrom the RAM via 16 data lines illustratively shown as 122. each lineinputs a data bit at the RAM timing rate of 1 bit per microsecond to theline store 120 which comprises eight 80-bit shift registers operated inparallel. Of course, other length shift registers may be employeddepending only upon the data present in line store 120, which data iscoupled first to a byte switch 124 which divides the l6-bit input intotwo 8-bit character bytes and alternately parallel transfers the datacontained by bits 1 throgh 8 and 9 through l6 via lines 126 to the linestore 120. The timing for the alternate word transfer is provided by theraster timing via line 128 and these data pulses occur during entry ofthe next row of data from the random access meory 106 into the linestore.

in the preferred embodiment row store employs dynamic shift registers,arranged such that any stoppage of clock pulses will not be ofsufficient duration to result in loss of data. Normally, data isrecirculated in registers 120 a number of times equivalent to the numberof line scans of the raster necessary to write a character, typicallythis is 7 to 9 times, although in the present embodiment recirculationoccurs 9 times. Clock pulses from the raster timing are inputted to therow store 120 via line 130 to clock data out of row store 120 and intothe character generator read only memory 132 via seven linesillustratively shown at 134 at the clock rate. The data is also ofcourse recirculated in row store 120 during the parallel transfer fromregister 120 to read only memory 132.

Read only memory 132 converts the 7-bit character code into video pulseswhich represent the various character portions or slices as illustratedby FIG. 8. Seven rows of dots or character slices are required for thegeneration of each displayed character. Read only memory 132 may, forexample, comprise three Intel MOS LS1 ROM memory type l30l withself-contained gating. The read only memory timing is received at ROM132 from the timing generator on line 140. The read only memory may becomprised of several chips ofintegrated circuitry as described withrespect to FIG. 11, with each chip section of read only memory 132accepting eight input address lines which can produce 32 characters fora 96 character total when the memory sections are employed. For each ofthe 256 locations in each chip, 8 output data bits are available with 7bits generating one line of data per character and with the eighth bitused for shifting the character code. Lines 136, the character sliceaddress lines, input a 3 bit address code from the read only memorytiming as previously described.

This 3 bit address code is coupled to read only memory 132 as additionalcoding bits along with the 5 bit charcter code on line 134 to comprise astandard 8 bit data code. While the internal gating in memory 132 isstandard, the unitary 8 bit code in actuality derives from separatesources, with the 3 bit slice counter portion on line 136 being cyclicaland the 5 bit portion on line 134 being random. Thus, characteraddressing and slice selection and incrementing is simplified to asingle decoding operation by read only memory 132.

The address lines 136 are inputted to the read only memory one bit priorto character display upon receipt of an appropriate timing signal vialine from the ROM timing. Character codes for 32 different charactersare inputted to the memory 132 via lines 134 as previously described.Output data from the read only memory 132 is parallel transferred to an8-bit shift register 142 with 7 dot bits going into register 142 and theeighth dot bit located in the seventh data bit location, with the shiftbit being coupled to flip-flop 144 with the shift occurring duringintercharacter time. A video clock 146 shifts the data serially out ofregister 142 to one of two paths, one of which path 148 is delayed bydelay line 149 for one-half dot bit time which is typically 40nanoseconds with the character dots being spaced about 40 nanosecondsapart. The alternative path 152 couples output data from register 142 togate 154 at which point the data is gated to the video output gate 156which is an OR gate for mixing the blanking signals. Depending upon thestate of the eighth shift bit for each character portion or slice, datais either delayed or undelayed by coding the shift bit either a logicalone or a logical zero, and a one-half dot shift is effected such thatselected dots in selected slices of a character are delayed with theeffect of producing character enhancement as illustrated by theexemplary letter A in H08. 8 and 9 in which dots in the second, fourthand sixth character slices are effectively shifted to produce morerealistic characters when the shift bits are at a logical one.

A single cursor bit is coupled to the random access memory I06 in eitherthe zero or eighth data bit position location which cursor bit is usedfor the generation of a movable cursor on the display screen. The cursorbit is coupled to byte switch 124 bia line 160 in the most significantbit position, and is then coupled to the line store 120 via gate 162into the most significant bit positin in one of the eight parallel shiftregisters of line store 120 in accordance with the address received frommemory 106. Whenever a logical one is detected by cursor generator 164which generator receives the cursor bit, either a zero when no cursor ispresent or a logical one, via line 166 from the line store, a cursor isgenerated and coupled through gate 156 to the video amplifier of theraster scan for display.

A switch 167 routes data from the random access memory back to the localcomputer accummulator when it is required that data be put back into thelocal computer such as when a keyboard function is selected. Switch 167is actuated by a signal from the memory select 118 via line 168 when theappropriate function key is selected. Blanking signals are gated throughgate 170 via the input buffer 172. The required dot matrix is generatedfrom a video which is normally blank except when data is written inaccordance with conventional blanking techniques.

The raster scan timing for synchronization of internal and externalclocking provided by the local computer, the keyboard interface, and theraster monitor, is provided by the raster scan timing which originatesin a crystal oscillator 180 of approximtely 24 megahertz which isdivided down to l2 megahertz in the vertical clock 146 and is thenfurther divided by 9 in divide by 9 counter 182 to synchronize thecharacter slices, each of which slices comprises nine dots with sevenactual dots and two intercharacter spaces. After division by counter 182the clock signal is again divided by 64 in an additional counter 184 toobtain line timing of 64 characters per line before coupling to theslice counter 186 which counts eight lines to give 3 bits out forgenerating a 3-bit code for selection of one of eight possible slicesper character. Frame counter 188 counts the number of lines per frame,typically 270 lines and is used to synchronize the video monitor withthe RAM timing.

Horizontal and vertical synchronization is generated by synchronizationgenerator 190 which synchronizes the vertical and horizontal pulses onthe cathode ray tube and determines when the horizontal and verticalsweeps start. Of course, vertical synchronization is determined by theframe counter output and horizontal synchronization by the output ofslice counter 186. For every 32 transfers from random access memory 106to byte switch 124 60 characters are transferred. This is timed byaddress counter 116 via gate 192 which couples the RAM timing to theaddress counter. The address counter is incremented 32 times by a divideby 32 counter 194 with coupling through gate 192 to address counter 116such that character addresses are generated between character rows.

Referring now to FIG. 11, certain of the more important waveformspresent in the block diagram illustrated by FIG. 10 are shown.

Waveform ll(a) is the horizontal retrace pulse train, which isapporximately l2.l microseconds. The read only memory strobing isillustrated by waveform b, which clocks data from line store 120 tomemory 132, and data is read out of the read only memory by waveform cand strobed into register 152 by waveform d. Shifting out of register152 to the dot shift circuitry occurs in accordance with timingproviding by waveform e. Data flowing along path 152, the unshiftedpath, is illustrated by waveformfwhile shifted data with a one half bitshift through delay line 149 is illustrated by waveform g. Waveform hclocks data from the output of the line store for recirculating whendata is read out to the memory 132, with shifting being accomplished inaccordance with waveform i. Waveforrnj illustrates the relationshipbetween the character generation time and horizonal retrace.

Referring now to FIG. 12, read only memory 132 is illustrated generallyat 250. A 5-bit character address code is inputted to memory 132 viadata lines 252 from line store 120, which code defines one of 32possible different characters per memory chip, for a total of differentpossible characters as there are three chips. Of course, more or lessread only memory may be utilized, depending only upon how many differentcharacters are required. A 3 bit timing code on lines 254 from slicecounter 186 is decoded by the memory 254 to select a particular row ofcharacters. in the present embodiment, there are l6 rows of displayedcharacters with nine lines per row from which characters may be formedwith six lines between rows for interrow spacing, and two character rowsfor vertical retrace for a total producing 270 lines, or horizontalraster scans per frame of data displayed-Each chip contains 32 8-bitlocations in which character information is stored. As

this data is clocked out a character slice at a time into register 142,the stop slice of all of the characters in a row, or one ninth of theindividual characters is displayed, These slices are incremented by thedivide by 15 slice counter 186 until all of the characters in one roware displayed, and the fifteenth line clocks counter 186 to change thecode on line 254 cyclically in order that character writing isincremented to the next row, and so on until the end of the frame, atwhich time the frame counter increments the row select code back to thefirst row for character refresh. A two bit chip select code is coupledto memory 132 from the line store along with the charcter address codein order that the correct 32 character memory section is adressed. Thiscode is coupled to the three memory sections in a conventional mannerthrough standard gating such as that provided by inverters 256 and ORgates 258.

While particular embodiments of the invention have been shown anddescribed, various modifications thereof will be apparent to thoseskilled in the art and therefore it is not intended that the inventionbe limited to the disclosed embodiments or to details thereof anddepartures may be made therefrom within the spirit and scope of theinvention as defined in the appended claims.

What is claimed is:

1. A visual display system comprising:

means for storing data representing at least a frame of characters to bedisplayed;

means coupled to said storing means for recirculating at least a portionof said data; means coupled to said recirculating means for generating aseries of signals representing each said char acter to be displayed;

means for selectively delaying at least a portion of said signals; and

means for displaying said characters.

2. A visual display system in accordance with claim 1 wherein saidsignal generation means comprises a read only memory.

3. A visual display system in accordance with claim 2 wherein said meansfor storing data comprises a random access memory.

4. A visual display system in accordance with claim 3 further includingmeans for dividing each of said characters to be displayed into aplurality of slices represented by a said serlepqfisignals each ofsaidslices being comprised of a plurality of dot signals.

5. A data communications and display system comprising:

a central processing unit;

means for coupling said central processing unit to a plurality ofcomputers at a plurality of locations, each of said computers having amemory;

means coupling a pluraliy of raster scanned alphanumeric displays toeach of said computers at each of said locations;

means at each of said displays for recirculating at least a portion ofdata received from the computer to which said display is coupled;

character generation means coupled to each of said recirculating means,said character generation means producing a video modulating signal forproducinb characters upon the display at which said recirculating meansis located, each of said characters comprising a plurality of dots, eachof said dots being located along a scan line of said display; and

means for selectively delaying said video modulating signal.

6. A data communications and display system in accordance with claim 5wherein said recirculating means recirculates data representing one rowof characters on said display.

7. ln combination:

data storage means for storing at least a plurality of alphanumericcharacter address codes;

means coupled to said data storage means for recirculating said addresscodes;

memory means coupled to said recirculating means for storingalphanumeric character data addressable by said address codes saidmemory means having an address input and data output;

means coupled to said memory means for sequentially selecting firstportions of said alphanumeric character data stored in said memory meansin response to said character address codes;

data utilization means coupled to the data output of said memory meansfor deriving a signal output from said first portions of saidalphanumeric character data; and

means for selectively delaying said signal output, said delaying meansoperating in response to second portions of said alphanumeric characterdata.

8. A visual display system in accordance with claim 4 wherein saiddisplaying means comprises a raster scanned cathode ray tube displaymeans having a plurality of raster scanned lines, each of said rasterscanned lines being produced continuously.

9. A visual display system in accordance with claim 8 wherein said dotsignals are produced along said raster scanned lines by modulating thelight intensity along said raster scanned line, said modulating beingaccomplished by said dot signals.

10. A visual display system in accordance with claim 9 wherein each dotwithin each slice which is to be shifted is shifted the same distancealong the said raster scanned line on which they are located by meansincluded within said delaying means.

11. A visual display system in accordance with claim 10 wherein saidsignal generating means comprises:

means for storing a first plurality of bits, said first plurality ofbits representing said dots for each of said characters; and

means for storing a second plurality of bits, said second plurality ofbits representing those slice dots which are to be shifted.

1. A visual display system comprising: means for storing datarepresenting at least a frame of characters to be displayed; meanscoupled to said storing means for recirculating at least a portion ofsaid data; means coupled to said recirculating means for generating aseries of signals representing each said character to be displayed;means for selectively delaying at least a portion of said signals; andmeans for displaying said characters.
 2. A visual display system inaccordance with claim 1 wherein said signal generation means comprises aread only memory.
 3. A visual display system in accordance with claim 2wherein said means for storing data comprises a random access memory. 4.A visual display system in accordance with claim 3 further includingmeans for dividing each of said characters to be displayed into aplurality of slices represented by a said series of signals each of saidslices being comprised of a plurality of dot signals.
 5. A datacommunications and display system comprising: a central processing unit;means for coupling said central processing unit to a plurality ofcomputers at a plurality of locations, each of said computers having amemory; means coupling a pluraliy of raster scanned alphanumericdisplays to each of said computers at each of said locations; means ateach of said displays for recirculating at least a portion of datareceived from the computer to which said display is coupled; charactergeneration means coupled to each of said recirculating means, saidcharacter generation means producing a video modulating signal forproducinb characters upon the display at which said recirculating meansis located, each of said characters comprising a plurality of dots, eachof said dots being located along a scan line of said display; and meansfor selectively delaying said video modulating signal.
 6. A datacommunications and display system in accordance with claim 5 whereinsaid recirculating means recirculates data representing one row ofcharacters on said display.
 7. In combination: data storage means forstoring at least a plurality of alphanumeric character address codes;means coupled to said data storage means for recirculatIng said addresscodes; memory means coupled to said recirculating means for storingalphanumeric character data addressable by said address codes saidmemory means having an address input and data output; means coupled tosaid memory means for sequentially selecting first portions of saidalphanumeric character data stored in said memory means in response tosaid character address codes; data utilization means coupled to the dataoutput of said memory means for deriving a signal output from said firstportions of said alphanumeric character data; and means for selectivelydelaying said signal output, said delaying means operating in responseto second portions of said alphanumeric character data.
 8. A visualdisplay system in accordance with claim 4 wherein said displaying meanscomprises a raster scanned cathode ray tube display means having aplurality of raster scanned lines, each of said raster scanned linesbeing produced continuously.
 9. A visual display system in accordancewith claim 8 wherein said dot signals are produced along said rasterscanned lines by modulating the light intensity along said rasterscanned line, said modulating being accomplished by said dot signals.10. A visual display system in accordance with claim 9 wherein each dotwithin each slice which is to be shifted is shifted the same distancealong the said raster scanned line on which they are located by meansincluded within said delaying means.
 11. A visual display system inaccordance with claim 10 wherein said signal generating means comprises:means for storing a first plurality of bits, said first plurality ofbits representing said dots for each of said characters; and means forstoring a second plurality of bits, said second plurality of bitsrepresenting those slice dots which are to be shifted.